Delay Aware Optimization of Multiplierless Linear Systems Using Two Term Continuous Arithmetic Extraction

We present a technique for redundancy elimination in multiplierless linear systems, such that the critical path of the computations is not increased. To the best of our knowledge this is the only method that combines common subexpression elimination and delay optimization in one single step. We assume that all the constant multiplications are decomposed into additions/subtractions and shift operations, to be evaluated using two input adders and hardwired shifts. Our technique can be used for linear systems consisting of any number of variables, with different arrival times. Experimental results show the superiority of our technique over other known methods. Index Terms – delay optimization, common subexpression elimination, DSP transforms, multiplierless filters, logic